1. Field of the Invention.
The present invention relates to the field of interrupt handling in computer systems and, more specifically, to interrupt handling in computer systems having multiple processors.
2. Prior Art.
A number of methods are known for handling interrupts in multiple processor computer systems. Generally, an interrupt may be defined as a response to an asynchronous or exceptional event that causes a processor to interrupt and save the current CPU status to allow for a later restart and causes a transfer to a specified routine called an interrupt handler. Typically, interrupts are assigned to classes, with a particular class including interrupts from similar devices or apparatus or interrupts which may be handled in a similar manner.
In a first known method, all interrupts from a particular class are assigned to and handled by a particular processor. Classes may be assigned to processors evenly over the processors in the computer system, may all be assigned to a single processor, or some other combination of assignment of classes to processors may be utilized.
In a second known method, a master processor initially services all interrupt requests and assigns the request to other processors or services the interrupt itself.
In a third known method, interrupts are serviced by processors in a round-robin fashion, in which a token is passed from processor to processor. When a processor completes service of interrupts, the token is passed to the next processor. The processor currently processing the token is assigned to process interrupts occurring while the processor possess the token.
In each of these methods of processing interrupts, an objective is to minimize impact on other system processing while processing the interrupts in an efficient manner. However, in each of the known methods, one processor may be idle while another processor which may not be idle is burdened with processing an interrupt. For example, in a processor utilizing the first method, fixed assignments of interrupt classes to particular processors, processor one may be idle. Processor two may be assigned to handle all interrupts occurring in Class A. Processor two may be currently busy executing a process when an interrupt occurs in Class A. In such a case, processor two must interrupt its processing of the current process to service the interrupt. At the same time, processor one remains idle. Similar inefficiencies occur in any interrupt handling system in which interrupts are assigned to a given processor during any given period of time without regard to the relative load placed on that processor.
Therefore, what is desired is an interrupt handling apparatus and method in which interrupts are assigned to the processor in the system which is currently least busy. It is further desired to provide an apparatus and method in which interrupts of a same class may be assigned to the same processor where that processor has already loaded the appropriate interrupt handling routines.